# Can Silicon Spin Qubits Scale Through Standard Chip Fabs?

Eight qubits, one standard 300 mm CMOS wafer, no loss in [coherence time](https://quantumintel.tech/glossary/coherence-time) — that is Diraq's answer, published today in *Nature Communications*. The Australian quantum startup has successfully operated an eight-qubit silicon spin-qubit array fabricated at imec using the same industry-standard CMOS process that produced its two-qubit result, which exceeded 99% [gate fidelity](https://quantumintel.tech/glossary/gate-fidelity), reported in September 2025. The fourfold increase in array size came with no degradation in coherence or control performance, and critically, without a proportional increase in sensor count, wiring density, or thermal load. Diraq is now targeting devices with hundreds of qubits as an immediate next step, with thousands of qubits by 2029 and more than one million qubits by 2031 on its public roadmap.

For investors and enterprise buyers evaluating quantum hardware bets, the significance is straightforward: Diraq has now demonstrated multiplicative scaling on a single, commercially established wafer platform in under twelve months. No custom fab process. No exotic materials. The same foundry infrastructure that produces today's classical chips could, if Diraq's trajectory holds, produce utility-scale quantum processors within this decade.

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## What the Nature Communications Paper Actually Shows

The paper, titled *"Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device,"* extends Diraq's 2025 Nature result by a factor of four in array size. The eight qubits are arranged as four pairs in a linear array, each individually addressed and tuned. According to the source material, single-qubit coherence times are comparable to — and at the upper end of — the state of the art for the silicon spin-qubit platform.

Two technical claims deserve particular scrutiny:

**Readout scaling efficiency.** The paper reports that scaling from two to eight qubits did not require a significant increase in sensor count, wiring density, or thermal load. For anyone who has watched superconducting transmon systems balloon in physical complexity as qubit counts rise, this is a meaningful claim. If the readout overhead scales sub-linearly with qubit count, the path to dense, compact arrays becomes architecturally credible rather than aspirational.

**Fabrication fidelity consistency.** The 2025 two-qubit devices consistently exceeded 99% fidelity — a figure that clears the [error threshold](https://quantumintel.tech/glossary/error-threshold) typically cited as a necessary (though not sufficient) condition for practical quantum error correction. The current paper claims this performance is maintained in the eight-qubit device. The published data in *Nature Communications* will allow independent researchers to verify whether that claim holds across all eight qubits uniformly, or whether it reflects best-case pairs — a distinction that matters enormously for QEC overhead calculations.

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## The CMOS Bet: Why Foundry Fabrication Changes the Economics

Diraq's core thesis is that silicon spin qubits built on CMOS infrastructure eliminate the manufacturing bottleneck that constrains every other qubit modality. Trapped-ion systems require precision ion traps and ultra-high vacuum apparatus. Superconducting qubits need dilution refrigerators and custom Josephson junction deposition. [Neutral atom qubits](https://quantumintel.tech/glossary/neutral-atom-qubit) require sophisticated optical tweezer arrays. None of these are built at scale in existing chip fabs.

Silicon spin qubits — specifically Diraq's SiMOS architecture, developed originally by founder and CEO Andrew Dzurak at UNSW Sydney — encode quantum information in the spin states of individual electrons confined in silicon quantum dots. The gate structures that confine those electrons are, structurally, close relatives of classical MOSFET transistors. That is what makes imec's 300 mm CMOS line a viable fabrication platform rather than merely a convenient analogy.

The semiconductor industry has spent roughly six decades refining yield, uniformity, and throughput on silicon wafers at this scale. Diraq is effectively claiming access to that entire infrastructure inheritance. If true, the cost and time-to-scale curves for silicon spin qubits look fundamentally different from those facing photonic or superconducting competitors.

The counter-argument, which Diraq's data must eventually address, is qubit uniformity at scale. Classical CMOS devices tolerate a distribution of transistor characteristics because digital logic is binary and tolerant of variation within a wide window. Quantum operations are far more sensitive — small variations in quantum dot geometry or gate oxide thickness translate directly to qubit frequency disorder and cross-talk, both of which degrade [fault-tolerant quantum computing](https://quantumintel.tech/glossary/fault-tolerant-quantum-computing) performance. Eight qubits is not yet the scale at which that uniformity challenge becomes statistically brutal. Hundreds of qubits will be.

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## Roadmap Credibility: Nine Months From 2 to 8 Qubits

CEO Andrew Dzurak's public statement frames the cadence explicitly: "Nine months ago, we showed the world that our silicon qubits could be built reliably in imec's 300 mm CMOS line. Today, we have scaled the size of the array using exactly the same process, with no compromise in coherence. This is the cadence we need to reach utility scale."

The roadmap numbers Diraq has published are aggressive by any measure: hundreds of qubits as an immediate target, thousands by 2029, more than one million by 2031. For context, the jump from 8 to hundreds is not a 10× step — it is more than an order of magnitude, and the jump from hundreds to one million is three orders of magnitude beyond that. Each step introduces new engineering challenges that cannot be fully predicted from smaller-array results.

That said, the nine-month cadence from two to eight qubits on the same wafer process is a concrete, verifiable data point that lends some credibility to the company's claim of industrial-style scaling rhythm. No other silicon spin-qubit player has published a comparable foundry-fabrication milestone at this scale to date, though [Intel Quantum](https://quantumintel.tech/companies/intel) has pursued a parallel silicon spin-qubit program on its own CMOS process for several years.

The physical footprint argument Diraq makes — that a utility-scale quantum computer based on this architecture would occupy no more physical space than the current eight-qubit device — is plausible in principle given that millions of classical transistors fit on a chip the size of a fingernail. But it conflates die area with total system footprint. Cryogenic cooling, control electronics, and readout hardware still occupy significant rack space regardless of how many qubits fit on the silicon die.

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## Industry Implications

The publication arrives at a moment when the quantum hardware field is fragmenting into modality camps with increasingly distinct commercial trajectories. Superconducting systems from [IBM Quantum](https://quantumintel.tech/companies/ibm) and [Google Quantum AI](https://quantumintel.tech/companies/google-quantum-ai) dominate cloud access today. Trapped-ion systems from [Quantinuum](https://quantumintel.tech/companies/quantinuum) and IonQ lead on [gate fidelity](https://quantumintel.tech/glossary/gate-fidelity) benchmarks. Neutral atom arrays from QuEra and others are demonstrating [logical qubit](https://quantumintel.tech/glossary/logical-qubit) operations. And photonic approaches from [PsiQuantum](https://quantumintel.tech/companies/psiquantum) share Diraq's foundry-fabrication thesis but use a different physical substrate entirely.

Silicon spin qubits have historically lagged in qubit count compared to superconducting and trapped-ion systems, but the CMOS compatibility argument gives them a credible long-range scaling story that other modalities struggle to match. Today's result does not close that gap — eight qubits is not competitive with current superconducting processors on any performance benchmark — but it validates the fabrication thesis at a new scale, which is the necessary prerequisite for everything that follows.

For enterprise buyers, the practical implication is that silicon spin-qubit hardware is not yet a near-term procurement option. For investors and strategic evaluators, the question is whether the foundry-scaling thesis survives the transition to hundreds of qubits with uniformity and yield intact. The next Diraq publication will be more informative than today's.

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## Key Takeaways

- Diraq published eight-qubit operation of a 300 mm CMOS-fabricated silicon spin-qubit array in *Nature Communications* on July 9, 2026.
- The array was fabricated at imec using the same process that produced the 2025 two-qubit result, which exceeded 99% gate fidelity.
- Fourfold scaling from two to eight qubits was achieved in under nine months with no reported degradation in coherence or control quality.
- Readout architecture scaled sub-linearly — no significant increase in sensor count, wiring density, or thermal load was required.
- Diraq's public roadmap targets hundreds of qubits next, thousands by 2029, and more than one million qubits by 2031.
- The CMOS foundry thesis is validated at a new scale, but uniformity challenges at hundreds-to-thousands of qubits remain the central unresolved question.
- Physical footprint claims for utility-scale devices conflate die area with total system size, including cryogenics and classical control electronics.

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## Frequently Asked Questions

**What did Diraq demonstrate in its July 2026 Nature Communications paper?**
Diraq demonstrated the operation of an eight-qubit silicon spin-qubit array fabricated at imec using a standard 300 mm CMOS semiconductor process. The result represents a fourfold increase in array size from the company's 2025 two-qubit result, achieved on the same wafer platform with no reported loss in coherence or gate control quality.

**What gate fidelity did Diraq's previous silicon qubits achieve at imec?**
Diraq's September 2025 two-qubit devices, fabricated at imec on the same 300 mm CMOS platform, consistently exceeded 99% fidelity — a threshold relevant to quantum error correction requirements.

**Why does CMOS fabrication matter for quantum computing scalability?**
Standard CMOS fabrication infrastructure, as used in classical semiconductor manufacturing, offers mature yield control, high throughput, and established supply chains. Silicon spin qubits compatible with this process can in principle leverage existing foundry capacity rather than requiring new, quantum-specific manufacturing facilities — a potential advantage for cost and scale compared to modalities that require custom fabrication.

**How does Diraq's silicon spin-qubit approach compare to superconducting or trapped-ion systems?**
Superconducting systems currently lead in deployed qubit count and cloud accessibility. Trapped-ion systems lead on gate fidelity benchmarks. Silicon spin qubits remain behind on raw qubit count but carry a stronger theoretical case for long-range scalability through CMOS manufacturing. At eight qubits, Diraq's system is not yet competitive on performance metrics, but the fabrication milestone is the foundation for the scaling argument.

**What are the key risks to Diraq's roadmap toward thousands of qubits?**
The primary technical risk is qubit uniformity at scale. Small variations in quantum dot geometry and oxide thickness — tolerable in classical CMOS but potentially damaging to quantum operations — become statistically harder to control as array sizes grow. The transition from eight to hundreds of qubits will be the first genuine test of whether imec's process delivers sufficient uniformity for large-scale quantum operation. Yield, cross-talk, and classical control electronics overhead are additional challenges that become more acute at higher qubit counts.