# Can EUV Lithography Make Silicon Spin Qubits Manufacturable at Scale?

The answer, based on results just published by Imec and Diraq, is an emphatic yes — with caveats worth examining carefully.

Researchers at Imec (Leuven, Belgium) and Diraq (Sydney, Australia), working alongside multiple university collaborators, have fabricated silicon metal-oxide-semiconductor (SiMOS) spin qubits using extreme-ultraviolet (EUV) lithography — the same patterning technology that underpins leading-edge classical semiconductor production — and measured [gate fidelity](https://quantumintel.tech/glossary/gate-fidelity) values of 99.9% for state preparation and measurement (SPAM), 99.8% for single-qubit gates, and 99.5% for two-qubit gates across four characterized double-dot systems. Exchange turn-on characteristics were reproducible across devices in the range of 1.2 to 1.8 µeV. These numbers matter because they sit close to the [error threshold](https://quantumintel.tech/glossary/error-threshold) required for practical [fault-tolerant quantum computing](https://quantumintel.tech/glossary/fault-tolerant-quantum-computing) — and they were achieved not in a bespoke academic cleanroom but in a semiconductor pilot line using tooling already deployed at commercial scale.

The significance here is not simply high fidelity. Labs running electron-beam (e-beam) lithography have demonstrated comparable single-device performance before. What distinguishes this result is that EUV exposes an entire reticle field simultaneously, enabling throughput and overlay control that serial e-beam patterning cannot match. For a technology that needs to scale to thousands and eventually millions of physical qubits, the fabrication method is as consequential as the qubit numbers themselves.

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## Why EUV Changes the Scalability Calculus for Spin Qubits

SiMOS quantum dots are among the most compact qubit implementations under active development. Effective electron confinement and strong exchange coupling — the interaction that enables two-qubit gates — require gate pitches below 10 nanometers. Achieving that precision consistently across a full wafer, across multiple devices, and across successive patterning layers is where e-beam lithography has historically struggled.

E-beam tools write patterns serially, pixel by pixel. At the pitches SiMOS demands, overlay errors between successive layers compound, and throughput collapses. Both problems worsen as qubit arrays grow. EUV addresses this structurally: the entire pattern is exposed in one shot per field, and modern EUV scanners — the kind already running in high-volume fabs — offer sub-nanometer overlay control as a baseline specification.

The Imec–Diraq team reports room-temperature gate-to-gate leakage yield across a full wafer, alongside sub-nanometer control of critical gate dimensions and reproducible oxide thickness and inter-layer overlay. These are not qubit-specific metrics; they are the standard quality indicators that semiconductor process engineers use to qualify a production-ready process. Seeing them applied to qubit characterization is itself a signal of how seriously this collaboration is treating manufacturability as a first-class constraint.

Gate set tomography (GST), a rigorous characterization protocol that reconstructs the full error model for each gate operation rather than relying on simpler benchmarking proxies, was used to validate performance across four double-dot systems realized within two triple-quantum-dot devices. The consistency of results across devices — particularly the 1.2 to 1.8 µeV range for exchange turn-on — is the kind of uniformity that an eventual [logical qubit](https://quantumintel.tech/glossary/logical-qubit) architecture built on surface codes would require. Variance in exchange coupling across a qubit array translates directly into variance in two-qubit gate fidelity, which translates into elevated logical error rates.

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## What the Numbers Mean — and What They Don't Prove Yet

The 99.5% two-qubit gate fidelity figure demands context. Surface code threshold estimates typically sit in the range of 99% physical gate fidelity, though exact numbers depend heavily on error model assumptions, decoding overhead, and the specific QEC protocol. At face value, 99.5% clears that bar. But clearing a threshold in a two-qubit system characterized under controlled conditions is categorically different from maintaining it across a multi-qubit array where crosstalk, charge noise, and variability accumulate.

The team characterized four double-dot systems. That is enough to demonstrate process reproducibility as a proof of concept; it is not enough to characterize how fidelity degrades as qubit count increases, or to quantify the crosstalk penalty in a densely packed array. Those are the next questions this line of work will need to answer.

It is also worth noting that the source material describes results from a pilot line, not a full production fab. The gap between a semiconductor pilot line and high-volume manufacturing is real — in yield, in process maturity, and in cost per device. [Intel Quantum](https://quantumintel.tech/companies/intel) has been pursuing a similar thesis — leveraging classical fab infrastructure for silicon spin qubits — for several years, and the engineering challenges of bridging that gap have proven substantial even for a company with direct access to world-class fabs.

None of this diminishes what Imec and Diraq have demonstrated. It contextualizes it: this is a critical proof point in the fabrication argument for silicon spin qubits, not a finished manufacturing solution.

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## Industry Implications: The Fab-Compatible Qubit Thesis Gets Its Strongest Data Point Yet

The broader strategic argument for silicon spin qubits has always rested on two pillars: compatibility with existing semiconductor infrastructure, and the potential for density that no other physical qubit platform approaches at comparable fidelity. The first pillar has been theoretical for most of the field's history. This result makes it empirical.

For enterprise buyers and investors evaluating quantum hardware platforms, the EUV result shifts the probability distribution on silicon spin qubit timelines. The fabrication bottleneck — specifically the overlay and throughput limitations of e-beam lithography — has been cited as a key risk factor distinguishing silicon spin qubits from superconducting transmon qubits, which are fabricated using optical lithography processes that are already industrially mature. That risk has now been materially reduced.

For competing platforms, the implications are worth noting. Superconducting qubit leaders have built significant leads in qubit count and system-level integration. Trapped-ion and neutral atom approaches offer architectural advantages in connectivity and mid-circuit measurement. But neither class of system can point to a fabrication pathway that is, in principle, directly compatible with TSMC or Samsung fab tooling. If silicon spin qubits can sustain and extend these fidelity results at scale, the long-run cost and density economics shift substantially in their favor.

Diraq, the Sydney-based startup commercializing SiMOS spin qubit technology, and Imec, whose role as a semiconductor research consortium gives it direct relationships with the foundry ecosystem, are well-positioned to push this line of work toward a commercial process. The specific timeline for that transition remains unclear from the available source material.

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## Key Takeaways

- **99.8% single-qubit gate fidelity** and **99.5% two-qubit gate fidelity** measured via gate set tomography in EUV-fabricated SiMOS spin qubits — results achieved in a semiconductor pilot line, not a bespoke lab setup.
- **Exchange turn-on uniformity of 1.2 to 1.8 µeV** across four double-dot systems demonstrates the fabrication reproducibility that qubit array scaling requires.
- **EUV lithography resolves the throughput and overlay limitations of e-beam lithography** for sub-10nm gate pitches, addressing a structural scalability barrier for silicon spin qubits.
- **Imec (Leuven) and Diraq (Sydney)** led the work, with university collaborators; the pilot-line setting signals industrial intent, not just academic demonstration.
- **Two-qubit fidelity nominally clears surface code threshold estimates**, but scaling from four characterized double-dots to a multi-qubit array with maintained fidelity remains undemonstrated.
- This result strengthens the strategic case for fab-compatible qubit platforms, but the gap from pilot line to high-volume production remains a genuine engineering challenge.

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## Frequently Asked Questions

**What is EUV lithography and why does it matter for quantum computing?**
Extreme-ultraviolet lithography is the patterning technology used to manufacture advanced classical chips, exposing entire circuit patterns in a single step using very short-wavelength light. For SiMOS spin qubits, which require gate pitches below 10 nanometers, EUV provides the overlay precision and throughput that serial electron-beam lithography cannot. The Imec–Diraq result is the first strong evidence that EUV can produce high-fidelity spin qubits reproducibly across a full wafer.

**What gate fidelities did Imec and Diraq achieve?**
Gate set tomography across four double-dot systems showed 99.9% for SPAM (state preparation and measurement), 99.8% for single-qubit gates, and 99.5% for two-qubit gates. Exchange turn-on characteristics were reproducible in the 1.2 to 1.8 µeV range across all characterized devices.

**Are these fidelity numbers sufficient for fault-tolerant quantum computing?**
The two-qubit fidelity of 99.5% nominally exceeds commonly cited surface code threshold estimates. However, fault tolerance requires sustaining these numbers across large qubit arrays under realistic operating conditions, including crosstalk and charge noise from neighboring qubits — a challenge that four characterized double-dots does not address.

**How does SiMOS compare to superconducting transmon qubits?**
SiMOS spin qubits operate at millikelvin temperatures like transmons but offer significantly higher potential qubit density and direct compatibility with silicon semiconductor manufacturing processes. Transmon-based systems currently lead in qubit count and system integration maturity. SiMOS devices are smaller and may offer long-term fabrication cost advantages, but have fewer qubits demonstrated in integrated arrays to date.

**What is Diraq's role in this research?**
Diraq is a Sydney-based quantum computing company commercializing SiMOS spin qubit technology. The company collaborated with Imec's semiconductor pilot line in Leuven to demonstrate that EUV lithography can produce high-fidelity SiMOS qubits, combining Diraq's qubit expertise with Imec's semiconductor fabrication infrastructure and industry relationships.