# Can Cat States Replace Complex Resource States in LDPC Fault-Tolerant Quantum Computing?

A new paper from Mark Webster and Nicolas Delfosse, posted to arXiv on July 17, 2026, answers that question with a decisive yes — and the performance numbers are striking. By replacing the complex resource states that prior work required for logical measurements in quantum LDPC codes with simple [cat states](https://quantumintel.tech/glossary/cat-qubit), the authors report a speed-up of nearly **3× over Viterbi measurements** for 20 simultaneous commuting logical operator measurements, scaling to **up to 74×** for random [Clifford circuits](https://quantumintel.tech/glossary/clifford-gates) when combined with a new variant of partial error correction. Even non-Clifford gates benefit: Toffoli gate operations see a speed-up of up to **5×**. The results are demonstrated numerically on two specific LDPC codes — Q70 and Q102 — drawn from the walking cat architecture. For the [fault-tolerant quantum computing](https://quantumintel.tech/glossary/fault-tolerant-quantum-computing) field, this matters because LDPC codes already offer dramatically lower qubit overhead than the surface code, and the prior assumption was that you paid for that efficiency with slower or more complex logical operations.

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## The Core Problem: LDPC Codes Are Qubit-Efficient but Operationally Awkward

Quantum LDPC (low-density parity-check) codes have become one of the most actively discussed approaches to fault-tolerant QEC because of their high encoding rate — meaning they can protect many [logical qubits](https://quantumintel.tech/glossary/logical-qubit) with substantially fewer physical qubits than surface code architectures require. That overhead reduction is not academic: in practical fault-tolerant systems, the ratio of physical to logical qubits dominates total hardware cost.

The tradeoff has always been operational complexity. In the surface code, logical operations benefit from a relatively clean geometric structure — gates can be applied patch-by-patch with well-understood resource requirements. In LDPC codes, multiple logical qubits are packed into a single code block, and performing simultaneous logical operations on them is non-trivial. The naive approach is slow; prior work tried to solve this by engineering complex, high-fidelity resource states specifically tailored to perform joint logical measurements efficiently. That approach works in principle but front-loads significant resource-state preparation overhead.

Webster and Delfosse argue this complexity is unnecessary. Their central claim: **cat states alone are sufficient** to achieve fast joint logical measurements across multiple qubits in an LDPC block, provided you design the measurement sequence correctly.

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## The Technical Contribution: Scheduler Codes and Joint Measurement Protocols

The paper's key technical ingredient is what the authors call a **scheduler code** — a classical coding structure that determines the sequence in which measurements are performed and enables decoding of all logical measurement outcomes jointly. This is not merely an engineering optimization; it is a new layer of classical code design that sits above the quantum error-correcting code itself and coordinates how information flows through the measurement process.

Previous cat-state-based measurement schemes were limited to a **single logical measurement** at a time. Webster and Delfosse generalize this to the joint measurement of **ℓ commuting logical operators simultaneously**, which is precisely what's needed to perform multi-qubit Clifford operations efficiently in an LDPC block.

The numerical validation uses two specific codes from the walking cat architecture: **Q70** and **Q102**. These are not toy examples — they represent realistic LDPC instances relevant to near-term fault-tolerant architectures exploring cat qubit hardware. For ℓ = 20 simultaneous logical operator measurements, the protocol achieves close to **3× speed-up over Viterbi measurements**, the prior state-of-the-art comparison point.

### Combining with CliNR Partial Error Correction

The larger speed-up figure — up to **74×** for random Clifford circuits — comes from combining the fast logical measurement protocol with a **new variant of the CliNR partial error correction scheme**. CliNR (the source does not expand the acronym beyond this) is a partial-QEC strategy that interleaves error correction with computation rather than running it as a fully separate stage. The specific variant introduced here is described as new, though the paper builds on prior CliNR work.

It is worth being precise about what "74×" means in context: this is a speed-up for the full random Clifford circuit execution, not for a single gate operation in isolation. The composition of faster joint measurements with smarter partial error correction compounds across circuit depth, which is why the aggregate figure is substantially larger than the per-measurement improvement.

For Toffoli gates — the canonical non-Clifford operation and a critical primitive for universal fault-tolerant computation — the protocol delivers up to **5×** speed-up. Non-Clifford gates are typically the bottleneck in fault-tolerant architectures because they cannot be implemented transversally in most codes and require magic state distillation or similar resource-intensive procedures. A 5× improvement here is notable, even if the mechanism and whether it reduces [magic state](https://quantumintel.tech/glossary/magic-state) consumption are details the abstract does not fully specify.

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## Why This Matters for the Broader LDPC Ecosystem

The walking cat architecture referenced in the paper is associated with a research direction that combines cat qubits — quantum systems engineered to have strongly biased noise (primarily phase-flip errors) — with LDPC codes designed to exploit that bias. Several hardware groups and startups are building toward this architecture, viewing it as a potential path to lower overhead fault tolerance.

The Webster-Delfosse result strengthens the case for this approach by directly attacking the operational speed argument that critics of LDPC codes often raise. If logical operations in LDPC blocks can be made nearly as fast as — or, in aggregate circuit terms, dramatically faster than — what naive analysis suggests, the qubit overhead advantage becomes less encumbered.

From a theoretical standpoint, the scheduler code concept is likely to generalize. The idea that a classical code can orchestrate the sequence of quantum measurements to simultaneously enable fast operation and decodable outcomes is a design pattern that other LDPC architectures — beyond the walking cat variant — could adopt. Whether the specific speed-up numbers transfer to other LDPC families is a question this paper leaves open, but the framework is not architecture-specific in its formulation.

**Analytical note:** The 74× figure will attract attention, and appropriately so — but readers should note it represents a best-case scenario for random Clifford circuits on the tested codes. Real workloads are not random Clifford circuits, and the speed-up for structured circuits targeting specific applications may be higher or lower. The 3× figure for the 20-operator measurement case is the more conservative and more directly hardware-verifiable number; it is also the one that will matter most for near-term experimental validation.

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## Key Takeaways

- **Cat states are sufficient**: Webster and Delfosse show that simple cat states — not complex, bespoke resource states — can enable fast joint logical measurements in LDPC codes, reducing resource-state engineering burden significantly.
- **3× speed-up per measurement batch**: For 20 simultaneous commuting logical operator measurements on Q70 and Q102 codes, the protocol nearly triples throughput compared to Viterbi measurement baselines.
- **74× for Clifford circuits**: When combined with a new CliNR partial error correction variant, the aggregate speed-up for random Clifford circuits reaches up to 74×.
- **5× for Toffoli gates**: Non-Clifford operations also benefit, a meaningful result given that Toffoli gates typically represent the dominant cost in fault-tolerant quantum computation.
- **Scheduler code is the key innovation**: A classical coding layer determines measurement sequencing and enables joint decoding — a generalizable concept beyond the walking cat architecture.
- **Validates LDPC as operationally viable**: The longstanding concern that LDPC codes trade qubit efficiency for operational slowness is directly addressed and substantially weakened by this result.

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## Frequently Asked Questions

**What are quantum LDPC codes and why do they matter for fault tolerance?**
Quantum LDPC (low-density parity-check) codes protect logical qubits using fewer physical qubits than the surface code because of their higher encoding rate. This overhead reduction is critical for practical fault-tolerant quantum computing, where physical qubit count directly drives hardware cost and complexity.

**What is a cat state and why is it used here?**
A cat state is a specific quantum superposition — in this context associated with cat qubit architectures that have strongly biased noise properties. Cat states are considered "simple" resource states relative to the highly engineered multi-qubit resource states that previous LDPC measurement protocols required. Webster and Delfosse show cat states are sufficient for fast joint logical measurements.

**What is the scheduler code introduced in this paper?**
The scheduler code is a classical coding structure that determines the sequence of quantum measurements in an LDPC block. It allows ℓ commuting logical operators to be measured jointly rather than sequentially, and enables all logical measurement outcomes to be decoded together. It is the central technical innovation enabling the speed-up results.

**Does the 74× speed-up apply to all quantum circuits?**
No. The 74× figure applies to random Clifford circuits on the Q70 and Q102 codes when the fast measurement protocol is combined with a new CliNR partial error correction variant. Real-world structured circuits will see application-specific speed-ups that may differ. The 3× figure for 20-operator measurements is a more conservative, directly measurable benchmark.

**How does this affect Toffoli gate performance?**
The protocol extends to non-Clifford gates, delivering up to 5× speed-up for Toffoli gates. Since Toffoli gates are essential for universal fault-tolerant computation and typically expensive to implement, this is a practically significant result, though the full resource accounting beyond speed-up is not detailed in the abstract.